1. introduction
this paper discusses three popular serial buses: jtag, spi, and i2c. a typical electronic product today will
have one or more serial buses in them.
using a serial bus in a system has many advantages over a parallel bus.
1. lower component cost
2. smaller printed circuit board
3. simplified design
4. typically, lower power consumption
the trade-off for these advantages is inherently lower data transfer rates than a parallel bus system. in serial
buses only one wire carries data into and/or out of the device. in some cases there is one signal for carrying
data into the device another different signal for carrying data out of the device. on the other hand in parallel
buses many signals transfer data simultaneously into and out of the device.
the following table provides a quick overview comparing these serial buses:
these three serial buses are described in the following sections.
2. spi
spi is an acronym forserial peripheral interfacebus. spi allows for full-duplex data transfers. typically, there
is only one bus master, all other spi devices are slaves. some vendors (example: xilinx™) provide a means
for spi bus arbitration, but this is not a requirement of the spi standard.
spi has a shared data bus. the master transmits data on the so signal line and receives data on the si
signal line, this allows the bus master to simultaneously transmit and receive data. all data transfers must
take place between the bus master and slaves. data transfers directly between two slave devices (flyby
transfers) are not allowed. the spi bus master signals are shown below.
sck spi bus clock output by spi bus master
si input data to bus master
so output data from bus master
figure 2.1 shows an example of an spi system with one bus master and three slave devices. the spi bus
master outputs an individual device select signal for each spi device slave.
figure 2.2 is an example of an spi read bus cycle of a spansion spi flash. for spansion spi devices,
data is sampled on the rising edge of sck and changes on the falling edge of sck.
the bus cycle events are as follows:
1. cs# is asserted low to select the flash.
2. the spi read command is send.
3. the internal 24-bit flash memory address is send.
4. the first flash data byte is read out.
in figure 2.2 at the left of the sck signal are shown the options ofmode 0andmode 3. depending on the
system sck should be high (mode3) when idle. in other systems sck it should be low (mode0) when idle.
in both mode 0 and 3 data is clocked in on the rising edge of clock and out on the falling edge of clock.
the spi bus is a loose standard. some devices can have a reversed sck polarity. note that some spi
devices can be connected in a daisy chain manner, but again this is not a requirement of the spi standard.
it is possible to daisy chain spi devices with the data output of the first spi device going into the data input
of the 2nd spi and so on. this paper does not discuss this. note that, like with jtag, none of the daisy
chained devices would have independent access to the bus master.
3. i2c
i2c is an acronym forinter icbus. i2c allows for multiple bus masters and flyby data transfers. standard i2c
can support data transfer up to 100 kbs. there is also fast i2c at 400 kbs and high speed i2c at 3.4 mbps.
the i2c bus master signals are shown below:
scl spi bus clock.
sda data
i2c bus has only two signals: scl and sda. they are both bi-directional and open collector. pull-up resistors
on scl and sda are required. scl is used for clock and wait. sda is used for address and data since there
is only one data line full-duplex cannot be supported.
figure 3.1 shows an example i2c system is shown below with two master/slave devices and two slave only
devices. the i2c bus does not have device select signals, but selects an i2c device by sending a device
select byte. therefore, all i2c devices must be preprogrammed with a unique i2c bus address before they
are used on the i2c bus. the i2c protocol supports up to 127 addressable devices.
3.1 i2c bus cycle
the i2c clock signal (sck) is generated by the current master, but all the slaves can hold the sck signal low
until they are ready to allow it to go high. in this way a rising sck is delayed until the slowest i2c device is
ready. figure 3.2 shows the transfer of a byte to a slave, the slave acknowledges the transfer, and then holds
down scl until it is ready for the next byte.
bus arbitration is done with the sda line. all of the potential bus masters simultaneously try to drive the sda
signal. when any bus master detects that they have driven a '1', but detected a '0' on the sda signal it has
lost the bus arbitration. it will immediately give up driving the sda signal and will go into slave mode incase it
was the addressed slave device.
4. jtag
the joint test action group (jtag) method of connection is the ieee standard #1149. it is also known as
“jtag boundary scan”. jtag is commonly used for the following applications:
1. board assembly test (verifies the connectivity of device pins to the pcb)
2. development tool (in-circuit emulator)
3. system debug (provides a “back door” into the system)
4. testing internal device circuitry (not be discussed here)
typically, jtag is a feature found in relatively high pin count devices, but not in low pin count devices. i2c
and spi can be found in both high pin count devices like microcontrollers and in low pin count devices like
a/d converters.
jtag uses four (plus an optional reset signal) wires to pass data through devices in a daisy chain. these
signals are shown below:
1. tdi (test data in) - daisy chained
2. tdo (test data out) - daisy chained
3. tck (test clock) - shared
4. tms (test mode select) - shared
5. trst (test reset) optional
figure 4.1 shows an example of a jtag circuit is shown in the following figure. there is a jtag controller
connection and three jtag devices.
a jtag controller is connected at the connector and it drives tck and tdi into device #1. the tdi data
eventually passed out of the device #1 tdo pin into device #2 and so on until the daisy chain is closed
back at the jtag controller at tdo. the buses signals tms and tck control the data transfer.
4.1 jtag bus cycle
data outputs change on the falling edge of tck and data is sampled on rising edge of tck. tms and trst
are not shown. data transfers with jtag are takes more clocks than the other serial buses, because in jtag
the data must pass sequentially through the devices in the chain. see figure 4.2.
5. summary
using serial buses instead of parallel buses can cut component costs, space, and power consumption. lower
system performance is typical, but could be acceptable in many applications. complete systems can be built
using either spi or i2c. jtag is typically used only during product development, manufacturing, or servicing.
colophon
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